1. Field of the Invention
The present invention relates to field programmable gate arrays (FPGAs). More particularly, the present invention relates to the configuration of resources connected to look up tables in an FPGA to enable greater configurability of the FPGA to meet user needs.
2. Description of the Related Art
FIG. 1 shows a block diagram illustrating components of a typical FPGA. As shown, the typical FPGA includes input/output (I/O) buffers, an array of configurable logic blocks (CLBs), switch matrix blocks (SBLOCKs) and configuration blocks (CBLOCKs).
The I/O buffers are arranged around the perimeter of the device and provide an interface between internal components of the FPGA and external package pins. Routing resource lines interconnect the I/O buffers, SBLOCKs, and CBLOCKs. The CBLOCKS include multiplexers to selectively provide signals from the routing resources to the CLBs.
As shown in FIG. 2, each CLB includes a series of look up tables (LUTs). The CLB of FIG. 2 in particular includes multiple three input LUTs, with two three input LUTs on each side of the CLB. Inputs to the LUTs are provided from a CBLOCK as shown. Outputs of the LUTs (not shown) may be selectively connected back to routing resources of the FPGA.
FIG. 3 illustrates the components typically utilized in a three input LUT as shown in FIG. 2. The three input LUT of FIG. 3 includes a 3 input decoder and 8 memory cells. The three input decoder decodes a signal provided to the LUT inputs to enable one of the 8 memory cells. The 8 memory cells have outputs connected to form a single LUT output. The memory cells can be programmed in any arbitrary manner to provide a desired LUT output based on inputs to the LUT. The table beneath the LUT illustrated in FIG. 3 illustrates programming of the memory cells of the LUT to provide a three input AND gate where only all "1" inputs to the LUT generate a "1" output.
FIG. 4 shows circuitry included in a CBLOCK section of FIG. 1 as connected to a 3 input LUT. As shown, the CBLOCK section includes multiple 8 to 1 MUXs, each receiving 8 inputs which are connectable to routing resources. Each of the MUXs of the CLB provide an output to the input of a LUT. Three programmable select bits are provided to each MUX in the CBLOCK to selectively provide one of the 8 inputs at its output.
Although only eight routing resources are shown in FIG. 1 providing possible connections to a single CBLOCK, up to 40 or more of the routing resources are typically provided along a path for connection to a single CBLOCK. The eight inputs of each MUX of the CBLOCK are then arbitrarily connectable to selected ones of the 40 or more routing resources.
FIG. 5 shows components of a 4 input LUT which may be included in a CLB, the 4 input LUT being composed of two 3 input LUTs 501 and 502, as shown in FIG. 2, along with a multiplexer (MUX) 503. As shown, the outputs of the 3 input LUTs 501 and 502 are connected to inputs of the MUX 503. A fourth input of the 4 input LUT provides a select signal to the MUX. The output of the MUX then provides the output of the 4 input LUT. The inputs of the 3 input LUT 501 are provided from the outputs of MUXs 511.sub.0-2 of a CBLOCK, while the inputs of the 3 input LUT 502 are provided by the outputs of MUXs 512.sub.0-2. With a 4 input LUT, the inputs of the 3 input LUT 501 will need to be identical to the input of 3 input LUT 502. Thus, the MUX 511.sub.0 must provide the same output as MUX 512.sub.0. Similarly, MUX 511.sub.1 must provide the same output as MUX 512.sub.1, and MUX 511.sub.2 must provide the same output as MUX 512.sub.2.
Similar to creation of a 4 input LUT from two 3 input LUTs in FIG. 3, two 4 input LUTs may be combined to form a 5 input LUT and will include four 3 input LUTs. With the CLB of FIG. 2 it can be seen that to obtain four 3 input LUTs, LUTs from two sides of the CLB must be utilized. To provide the same input signals to a 3 input LUT on one side of a CLB as are provided to a 3 input LUT on another side, which will be required to create a 4 input LUT, routing resources will need to be connected through an SBLOCK to the other side of the CLB to provide identical signals to MUXs connected on two sides of the CLB. Such an approach is undesirable, however, because routing resources are utilized which might be utilized for other purposes.